Title :
Branch-and-bound placement for building block layout
Author :
Onodera, Hidetoshi ; Taniguchi, Yo ; Tamaru, Keikichi
Author_Institution :
University of California
Keywords :
Circuits; Distributed computing; Geometry; Machinery; Optimization methods; Permission; Pins; Shape; Simulated annealing; Space exploration;
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
