Input-output-buffered ATM switches with delayed backpressure mechanisms

This paper presents a study of the effect of the delay in the back-pressure signal in an architecture with input-output-buffering with back-pressure control, on the switch performance. The exact value of the delay depends on the specific implementation of the back-pressure mechanism and the contention resolution policy. This involves the mechanism by which the information is broadcasted to the input ports. The study demonstrates that the delay in the back-pressure signal seriously affects the switch performance, since it could result in severe cell loss at the output ports. This cell loss at the output ports can be controlled by modifying the output queue management mechanism, i.e. by incorporating additional buffering at the output ports on top of the original output queue size. The amount of this additional buffering depends on the value of the delay in the back-pressure signal, and it does not seriously affect the size of the input buffers. Higher values of delay in the back-pressure signal do not adversely affect the cell loss at the input ports. This study also investigates the overall input and output buffer allocation policies to achieve acceptable cell loss performance for architectures with delayed back-pressure mechanisms