Design of low power CMOS PSRAM

Full custom design of 1KB CMOS PSRAM has been presented in this paper. Subsequent efforts putting refresh control on the DRAM have been implemented in pin out which is more compatible with small systems environment and hence more similar to the SRAM, which were designed for this environment. To achieve a compact power efficient pseudo static DRAM (PSRAM), it is designed and simulated. A PSRAM is a “one-transistor cell” dynamic RAM with non multiplexed addresses on chip in refresh circuit and an external refresh pin to control the refresh of the cell to maintain data in the memory. It is identical to SRAM except an extra refresh pin. The refresh of the memory cell occurs during the part of the cycle time when the memory is not being accessed. Here, 1K PSRAM is designed and simulated, its verification results are agreeing for pre and post layout simulations. TANNER EDA is used in the design.