Dynamic logic synthesis

Author

Yee, Gin ; Sechen, Carl

Author_Institution

Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

345

Lastpage

348

Abstract

A self-timed dynamic logic family, clock-delayed (CD) domino, was developed to provide non-dual-rail gates with inverting or non-inverting outputs. CD domino circuits are as easy to synthesize as static circuits and synthesis tools developed for static CMOS are used as part of a methodology for automating the design and synthesis of dynamic circuits. The methodology and CD domino´s characteristics are demonstrated in the synthesis of five MCNC combinational logic benchmark circuits. Simulations of extracted chip layouts for the circuits show speed improvement factors of 2.17 to 6.28 compared to their static CMOS counterparts

Keywords

MOS logic circuits; circuit layout CAD; clocks; combinational circuits; delays; logic CAD; CD domino circuits; MCNC combinational logic benchmark circuits; clock-delayed domino; dynamic logic synthesis; extracted chip layouts; inverting outputs; non-dual-rail gates; noninverting outputs; self-timed dynamic logic family; speed improvement factors; synthesis tools; CMOS logic circuits; Circuit synthesis; Clocks; Delay; Logic circuits; Logic design; Logic functions; Logic gates; MOS devices; Pulse inverters;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606644

Filename

606644