Design of a fast and efficient hardware implementation of a random number generator in FPGA

This research paper presents a fast and efficient hardware implementation of a pseudo-random number generator based on Lehmer linear congruential method. We demonstrate in this paper that how the introduction of application specificity in the architecture can deliver huge performance in terms of area and speed. The design has been specified in VHDL and is implemented on Xilinx FPGA device XC5VFX130T-3ff1738 and takes up only 23 slice LUTS. Our design generates 1 random number per cycle with a clock frequency of 502 MHz (502 million samples per second). The random numbers generated by our design are extensively verified against the C-code generated outputs for functional correctness.