A Reconfigurable, Generic and Programmable Feed Forward Neural Network Implementation in FPGA

This paper presents a new reconfigurable generic hardware implementation of multilayer feed-forward Neural-Networks (NNs) using field-programmable gate arrays (FPGAs). Implementations of feed-forward Neural-Networks face two major issues: 1) Limited resources available on the FPGA compared to the large number of multiplications required by Neural-Networks 2) The limited reusability of the design when applied to Neural-Network applications with different architectures. Our proposed implementation addresses both issues: The design reduces resource requirements by time-sharing. The time-shared resources are arranged in a scalable configurable processing unit. The scalability allows the user to implement the design with variable number of neurons-starting from only one neuron to the maximum number of neurons in any layer. The design also gives the user the ability to reconfigure it to solve different applications, this is performed with programming-like ease and flexibility and a GUI was implemented to allow automatic configuration of the design for different applications.