Title :
VLSI implementation of a DWT architecture
Author :
Acharya, Tinku ; Chen, Po-yueh
Author_Institution :
Intel Corp., Chandler, AZ, USA
fDate :
31 May-3 Jun 1998
Abstract :
In this paper, we presented the VLSI implementation and the simulation results of a systolic architecture for Discrete Wavelet Transform (DWT). This architecture is suitable for both decomposition and reconstruction of signals. The hardware utilization of the architecture is 100% unlike many other existing solutions in the literature
Keywords :
VLSI; digital signal processing chips; systolic arrays; wavelet transforms; DWT architecture; VLSI implementation; decomposition; discrete wavelet transform; reconstruction; systolic architecture; Clocks; Computer architecture; Discrete wavelet transforms; Hardware; Hydrogen; Image reconstruction; Low pass filters; Spline; Systolic arrays; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706896
