• DocumentCode
    2172187
  • Title

    Rewiring using IRredundancy Removal and Addition

  • Author

    Lin, Chun-Chi ; Wang, Chun-Yao

  • Author_Institution
    Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
  • fYear
    2009
  • fDate
    20-24 April 2009
  • Firstpage
    324
  • Lastpage
    327
  • Abstract
    Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alternative wire in the circuit such that the functionality of the circuit is intact. However, not every irredundant target wire can be successfully removed due to some limitations. Thus, this paper proposes a new restructuring technique, IRredundancy Removal and Addition (IRRA), which successfully removes any desired target wire by constructing a rectification network which exactly corrects the error caused by removing the target wire.
  • Keywords
    circuit optimisation; logic design; IRredundancy removal-and-addition; error correction; irredundant target wire; logic design optimization; rectification network; redundancy addition-and-removal technique; restructuring technique; rewiring technique; target wire removal; Boolean functions; Circuit faults; Circuit synthesis; Computer science; Design optimization; Error correction; Logic design; Logic testing; Redundancy; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
  • Conference_Location
    Nice
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-3781-8
  • Type

    conf

  • DOI
    10.1109/DATE.2009.5090682
  • Filename
    5090682