Numerical and experimental investigations of large IC flip chip attach

Because flip chips can achieve high electrical interconnect speed, high density, and low profiles, a team from the Fraunhofer Institute for Reliability and Microintegration in Berlin and from Georgia Tech undertake a study examining the extreme limits of flip chip input/output (I/O) capabilities and physical dimensions. Their starting point is a SIA estimate of memory requirements, based on Moore´s Law, for the year 2012. In order to study the limitations of flip chip technology the groups are working on both, advanced thermomechanical simulation and hands-on interconnection technology resulting in the design of four flip chips. They have the dimensions of 10×10 mm², 20×20 mm², 30×30 mm², and 40×40 mm². With these designs both, the simulation and the interconnection technology departments of Fraunhofer IZM start to evaluate the feasibility of flip chips beyond 20×20 mm²