Techniques for square ELT simulation: A comparative study

This work aims to study different analytical and numerical models to estimate effective W/L ratio considering transistors with enclosed gate geometry, suitable for implementation into standard Process Design Kits (PDK). Different geometries emphasizing the output (ID × VDS) and the transfer (ID × VGS) characteristics were studied. Besides estimating the aspect ratio, the source and the drain areas are also included in the equivalent transistor. The results show that, if considering DC simulations only, this modification does not significantly change the output behavior. The simulation technique was implemented using commercial available PDK´s and design and verification CAD tools targeted only toward the two-edged transistors, allowing automated ELT simulation.