Title :
Effects of Chip-Package Interaction on Mechanical Reliability of Cu Interconnects for 65nm Technology Node and Beyond
Author :
Uchibori, Chihiro J. ; Zhang, Xuefeng ; Ho, Paul S. ; Nakamura, Tomoji
Author_Institution :
Fujitsu Labs. of America Inc., Sunnyvale, CA
Abstract :
The impact of chip-package interaction (CPI) on the mechanical reliability of Cu low-k interconnects was investigated using a 3D multi-level sub-modeling method. The analysis was focused on the die attach process for Pb-free solder where a high thermal load will occur during solder reflow before underfilling to maximize the packaging effect. We compared first the CPI for a CVD-OSG (k=3.0) with MSQ (k=2.7) and spin-on polymer (k=2.7) to investigate how better material properties can improve interconnect reliability. Then the study was extended to porous MSQ (k=2.3) to examine CPI for the 65nm node and beyond. Finally, requirements of the mechanical properties of low-k ILD for improving interconnect reliability are discussed
Keywords :
chip scale packaging; copper alloys; integrated circuit interconnections; microassembling; nanotechnology; reflow soldering; reliability; 3D multilevel sub-modeling method; 65 nm; Cu; chip-package interaction; copper low-k interconnects; die attach process; inter layer dielectrics; interconnect reliability; lead-free solder; low-k ILD; mechanical reliability; nanotechnology; porous MSQ; solder reflow; spin-on polymer; Assembly; Dielectric materials; Finite element methods; Material properties; Materials reliability; Mechanical factors; Microassembly; Packaging; Polymers; Thermal stresses;
Conference_Titel :
Interconnect Technology Conference, 2006 International
Conference_Location :
Burlingame, CA
Print_ISBN :
1-4244-0104-6
DOI :
10.1109/IITC.2006.1648686
