Title :
Optimal Repeaters for Sub-50nm Interconnect Networks
Author :
Sekar, Deepak C. ; Venkatesan, Raguraman ; Bowman, Keith A. ; Joshi, Ajay ; Davis, Jeffrey A. ; Meindl, James D.
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA
Abstract :
Power consumed by interconnect repeaters is a serious concern for future ICs. Ways to tackle this issue such as unique optimization of repeater and logic transistor technologies, improved repeater insertion methods and 3D integration are discussed. These techniques reduce total power of a 22 nm 1.4 GHz low power combinational logic block by 55% with negligible performance and area overheads
Keywords :
combinational circuits; integrated circuit interconnections; integrated logic circuits; low-power electronics; repeaters; 1.4 GHz; 22 nm; 3D integration; combinational logic block; integrated circuits; interconnect networks; interconnect repeaters; logic transistor; low power electronics; optimal repeaters; repeater insertion; Capacitance; Delay; Integrated circuit interconnections; Logic gates; Optimization methods; Power dissipation; Power system modeling; Repeaters; Stochastic processes; Wire;
Conference_Titel :
Interconnect Technology Conference, 2006 International
Conference_Location :
Burlingame, CA
Print_ISBN :
1-4244-0104-6
DOI :
10.1109/IITC.2006.1648687
