A charge transfer-based high performance, ultra-low power PLL charge pump

This paper presents a high performance, ultra-low power scalable charge pump (CP) design for analog phase locked loops (PLLs). The compact CP circuit uses 4 minimum-sized transistor switches and a relatively small capacitor for transferring charge within the PLL to adjust the voltage controlled oscillator (VCO) frequency. Unlike the state of the art, the proposed CP design does not use current mirrors, has the ability to operate at very low voltages, and does not suffer from traditional mismatch errors due to its unique design. The fast switching action of the proposed CP allows for the use of a no-added delay D-flip flop (DFF) based phase-frequency detector (PFD) resulting in reduced PLL control loop delay and very low reference spurs in a PLL design. The proposed CP has been fabricated with a 1–10GHz PLL in TSMC all-digital 40nm CMOS process and physically tested with a variable 0.5–1.2V supply and a 50MHz–1GHz reference frequency. The charge pump has an active area of 0.0004mm², consumes on average 250pW power, and has a 0.1–0.3° phase error, depending on the PLL frequency of operation.