On-Chip Interconnect Networks at the End of the Roadmap: Limits and Nanotechnology Opportunities

Author

Naeemi, Azad ; Sarvari, Reza ; Meindl, James D.

Author_Institution

Georgia Inst. of Technol., Atlanta, GA

fYear

2006

fDate

5-7 June 2006

Firstpage

201

Lastpage

203

Abstract

Physical models are presented for single- and multi-wall carbon nanotubes. The models are used to quantify the performance enhancements that they can potentially offer if used as interconnects in GSI chips. For short lengths, mono-layer SWCN interconnects can lower capacitance by 50% whereas for long lengths SWCN-bundles can improve conductivity up to 100%. Conductivity of MWCNs increases with diameter if they are longer than a critical length of about 7 mum and decreases otherwise

Keywords

carbon nanotubes; electrical conductivity; integrated circuit interconnections; nanotechnology; GSI chips; electrical conductivity; multi-wall carbon nanotubes; nanotechnology; on-chip interconnect networks; single-wall carbon nanotubes; Capacitance; Carbon nanotubes; Copper; Inductance; Integrated circuit interconnections; Kinetic theory; Nanotechnology; Network-on-a-chip; Optical scattering; Particle scattering;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2006 International

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-0104-6

Type

conf

DOI

10.1109/IITC.2006.1648693

Filename

1648693

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2172614