Universal guideline for CMOS I/O signal integrity

Author

Gabara, Thaddeus ; Harrington, John ; Yan, Ran

Author_Institution

Bell Labs., Lucent Technol., Murray Hill, NJ, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

353

Lastpage

356

Abstract

BERT measurements have been used to characterize the digital receiver sensitivity during asynchronous ground bounce events and provide a reference point to establish a guideline for ground bounce criteria. Simultaneously switched digitally controlled output buffers improve the signal integrity of receivers over seven orders of magnitude when compared to conventional buffers. An algorithm with strong support of measurements has been used to develop a graphical approach to predicting the required power lead count of a packaged CMOS device

Keywords

CMOS logic circuits; asynchronous circuits; buffer circuits; circuit analysis computing; integrated circuit measurement; integrated circuit packaging; logic CAD; BERT measurements; CMOS; I/O signal integrity; asynchronous ground bounce events; digital receiver sensitivity; packaged device; power lead count; switched digitally controlled output buffers; CMOS technology; Circuit testing; Computational modeling; Digital control; Guidelines; Packaging; SPICE; Semiconductor device measurement; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606646

Filename

606646