DocumentCode
2172795
Title
The role of timing verification in layout synthesis
Author
Benkoski, Jacques ; Strojwas, Andrzej J.
Author_Institution
Carnegie Mellon University
fYear
1991
fDate
21-21 June 1991
Firstpage
612
Lastpage
619
Keywords
Circuit synthesis; Design automation; Equations; Integrated circuit layout; Integrated circuit synthesis; Libraries; Logic; Microelectronics; Process design; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location
IEEE
Print_ISBN
0-89791-395-7
Type
conf
Filename
979787
Link To Document