DocumentCode :
2172954
Title :
Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits
Author :
Deguchi, Yutaka ; Ishiura, Nagisa ; Yajima, Shuzo
Author_Institution :
Kyoto University
fYear :
1991
fDate :
21-21 June 1991
Firstpage :
650
Lastpage :
655
Keywords :
Boolean functions; Circuit analysis; Circuit simulation; Delay; Digital systems; Error analysis; Error probability; Logic circuits; Permission; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
Type :
conf
Filename :
979794
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2172954
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