A full function Verilog(R) PLL logic model

Author

Ashraf, Mohammad ; Kellgren, Tore ; Franz, Michael

Author_Institution

Toshiba America Electron. Components, San Jose, CA, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

357

Lastpage

360

Abstract

This paper describes the full function model of a phase-locked loop (PLL) in a logic simulator. In contrast to conventional models that bypass the PLL function, this Verilog model accurately represents all major characteristics of a PLL. It allows the simulation of the effect of the actual filter elements. It can accurately model clock deskew of a clock tree as well as synthesize other frequencies from the input clock. It produces a clock detect signal after a realistic lock sequence. The user has the option to add jitter to the PLL output. The model performs three orders of magnitude faster than an equivalent circuit model

Keywords

application specific integrated circuits; circuit CAD; clocks; digital phase locked loops; jitter; logic CAD; ASICs; Verilog; clock deskew; clock detect signal; clock tree; filter elements; full function model; input clock; jitter; lock sequence; logic model; logic simulator; phase-locked loop; Circuit synthesis; Clocks; Filters; Frequency synthesizers; Hardware design languages; Jitter; Logic; Phase locked loops; Signal detection; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606647

Filename

606647