Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies

Author

Lau, John ; Chang, Chris ; Lee, S. W Ricky

Author_Institution

Express Packaging Syst. Inc., Palo Alto, CA, USA

fYear

2000

fDate

2000

Firstpage

1360

Lastpage

1368

Abstract

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mechanics with finite element method. Furthermore, an empirical equation for predicting the thermal-fatigue life of flip chip solder joints is proposed

Keywords

chip scale packaging; crack-edge stress field analysis; finite element analysis; flip-chip devices; fracture mechanics; printed circuit manufacture; soldering; thermal stress cracking; crack propagation; crack tip stress intensity factor; finite element method; flip-chip package; fracture mechanics; printed circuit board assembly; solder joint reliability; thermal cycling; thermal fatigue life; wafer-level chip scale package; Chip scale packaging; Equations; Fatigue; Finite element methods; Length measurement; Printed circuits; Semiconductor device measurement; Soldering; Thermal stresses; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th

Conference_Location

Las Vegas, NV

Print_ISBN

0-7803-5908-9

Type

conf

DOI

10.1109/ECTC.2000.853386

Filename

853386