A digitally controlled oscillator for fine-grained local clock generators in MPSoCs

The evolution of technology into deep submicron domains leads to increasingly complex timing closure problems to design multiprocessor systems. One natural alternative is to resort to the globally asynchronous, locally synchronous paradigm (GALS). This work proposes a generic architecture for very low power- and area-overhead local clock generators (LCG) to drive individual modules of a multiprocessor, e.g. network on chip routers and other elements. As main original contribution it details the design of a digitally controlled oscillator (DCO), the core of the clock generator architecture. This DCO can produce at least 16 distinct frequencies between 117 MHz and 1 GHz and supports clock gating and glitch-free frequency changes. Its design is robust to PVT variations and takes less than 1000 µm².