DocumentCode
2173326
Title
SecBus: Operating System controlled hierarchical page-based memory bus protection
Author
Su, Lifeng ; Courcambeck, Stephan ; Guillemin, Pierre ; Schwarz, Christian ; Pacalet, Renaud
Author_Institution
STMicroelectron., Rousset
fYear
2009
fDate
20-24 April 2009
Firstpage
570
Lastpage
573
Abstract
This paper presents a new two-levels page-based memory bus protection scheme. A trusted operating system drives a hardware cryptographic unit and manages security contexts for each protected memory page. The hardware unit is located between the internal system bus and the memory controller. It protects the integrity and confidentiality of selected memory pages. For better acceptability the processor (CPU) architecture and the software application level are unmodified. The impact of the security on cost and performance is optimized by several algorithmic and hardware techniques and by a differentiated handling of memory pages, depending on their characteristics.
Keywords
cryptography; microprocessor chips; operating systems (computers); paged storage; system buses; CPU processor; SecBus; hardware cryptographic unit; internal system bus; memory controller; memory pages confidentiality; memory pages integrity; page-based memory bus protection; security context; trusted operating system; Application software; Computer architecture; Control systems; Cryptography; Hardware; Memory management; Operating systems; Protection; Security; System buses;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location
Nice
ISSN
1530-1591
Print_ISBN
978-1-4244-3781-8
Type
conf
DOI
10.1109/DATE.2009.5090729
Filename
5090729
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