DocumentCode
2173430
Title
VLSI design of echo cancelers for the HDSL system
Author
Bhattacharya, D. ; Subramanian, S. ; Shpak, D. ; Antoniou, A.
Author_Institution
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
fYear
1993
fDate
14-17 Sep 1993
Firstpage
1180
Abstract
A VLSI design of an echo canceler for a high bit-rate digital subscriber line transceiver is presented. The paper begins with the basic architecture and considers the operation of the various units in some detail. It concludes with simulation results which demonstrate that the data clock can be as high as 1.2 MHz
Keywords
CMOS integrated circuits; ISDN; VLSI; adaptive filters; data communication equipment; digital communication systems; digital filters; echo suppression; multiplexing; multiplexing equipment; subscriber loops; transceivers; 1.2 MHz; HDSL system; VLSI design; basic architecture; data clock; echo cancelers; high bit-rate digital subscriber line transceiver; simulation results; Clocks; Convergence; DSL; Design engineering; Equations; Finite impulse response filter; Hardware; Least squares approximation; Transceivers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1993. Canadian Conference on
Conference_Location
Vancouver, BC
Print_ISBN
0-7803-2416-1
Type
conf
DOI
10.1109/CCECE.1993.332467
Filename
332467
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