New high performance low power 4 bit full adder with reduce ground bounce noise

In this paper, the low power and reduce Ground Bounce noise 4 bit adder has been proposed. Full adder is the most important basic building block of digital circuits employing arithmetic operation. It is therefore necessary to make these systems more efficient to survive with high speed while consuming low power. As the speed of the circuit increases the most important unwanted parameter exhibited by the circuits is ground bounce noise. In this paper, we have proposed a modified 4 bit full adder based on using multi-threshold CMOS technique. Here we use forward body biased multimode (MTCMOS) technique to evaluate standby leakage current, power and ground bounce noise. All the simulation in this paper has been carried out using cadence virtuoso at 45 nm technology at various voltage and temperatures.