High power chip stacks with interleaved heat spreading layers

3-D chip packaging and optoelectronic array interconnect technologies can be combined to realize ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. Thermal management is becoming a key issue if the active volume is minimized. The use of CVD diamond layers as a thermal management tool for the implementation of 3D stacks has been demonstrated to allow up to 80 W power dissipation in densely packed stacks of less than 1 cm³