Title :
A new speculative addition architecture suitable for two´s complement operations
Author :
Cilardo, Alessandro
Author_Institution :
Dipt. di Inf. e Sist., Univ. degli Studi di Napoli Federico II, Naples
Abstract :
Existing architectures for speculative addition are all based on the assumption that operands have uniformly distributed bits, which is rarely verified in real applications. As a consequence, they may be disadvantageous for real-world workloads, although in principle faster than standard adders. To address this limitation, we introduce a new architecture based on an innovative technique for speculative global carry evaluation. The proposed architecture solves the main drawback of existing schemes and, evaluated on real-world benchmarks, it exhibits an interesting performance improvement with respect to both standard adders and alternative architectures for speculative addition.
Keywords :
adders; carry logic; parallel programming; adders; operands; speculative addition architecture; speculative global carry evaluation; twos complement operations; Added delay; Adders; Arithmetic; Circuits; Clocks; Computer architecture; Error correction; Frequency; Heart; Microprocessors;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
Print_ISBN :
978-1-4244-3781-8
DOI :
10.1109/DATE.2009.5090749