FPGA implementation folding

The ultimate focus of this paper is to design an efficient folded finite-impulse response (FIR) filters based on unique multiplier. The design is considered at the bit-level and the internal delays of the various multiplier array are fully exploited in order to reduce hardware complexity. The direct FIR filter form is considered. The ripple-carry, carry- save, Braun-array and Wallace-tree multiplier arrays are studied for the filter implementations. Partially folded architectures are also proposed which are implemented by cascading a number of folded FIR filters. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter based on the Wallace Tree multiplier. The comparison reveals that the proposed schemes require 10%-20% less hardware. Finally, efficient implementation of partially folded FIR filter circuits is presented when constraints in area, power consumption are given.