Design of a hardware accelerator for multi-layer maze routing in VLSI and its implementation on Virtex-II Pro FPGA

This paper proposes a new approach for the implementation of Lee´s grid-based Manhattan routing algorithm on Virtex-II Pro FPGA. The grid-based algorithm was also implemented using C Data Structures and a comparison is drawn between the two approaches. A hardware accelerator for an 8 x 8 x 4 grid has been successfully implemented and tested on Xilinx Virtex-II Pro FPGA. Performance of hardware accelerator shows speed-up of 40-60% over software implementation for an 8 x 8 x 4 grid. The success of this approach demonstrated here favors further research to develop larger size arrays with multi-layer routing on high end FPGAs and to evaluate the performance of these designs.