An exclusion algorithm for reduction of bus transitions in low power VLSI

In VLSI design using deep sub micron technology, the bus energy reduction has become more and more important. As technology is scaling down, the increased interconnect wire aspect ratio and the reduced spacing between the individual wires within the bus result in increased cross coupling capacitances. They also increase cross talk noise and power dissipation in the data buses. In addition there is also a self- capacitance introduced between two adjacent data lines. We have developed an exclusive encoding algorithm that reduces the coupling transitions (1 to 0 or 0 to 1 state transition) and also the self-transitions in the data buses. The technique requires 2 extra bits for sending coding information regardless of the bit width of the bus and does not assume anything about the nature of the data.