An analytical timing-driven algorithm for detailed placement

Most of recent placement algorithms are driven to HPWL minimization and routability improvement. Although timing-closure is one of the most essential aspect of the synthesis flow, few methods are currently targeting delay reduction by handling critical paths during global or detailed placement. In this work, we adapted a global placement algorithm to perform timing-aware incremental detailed placement. The analytical algorithm employed reduces, on average, by 31% and 43%, respectively, the WNS and TNS violations on all circuits and all critical path configurations after clock skew optimization, based on ICCAD 2014 benchmarks.