DocumentCode :
2174583
Title :
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Author :
Mohammadzadeh, Naser ; Mirsaeedi, Minoo ; Jahanian, Ali ; Zamani, Morteza Saheb
Author_Institution :
Dept. of Comput. Eng., Amirkabir Univ. of Technol., Tehran
fYear :
2009
fDate :
20-24 April 2009
Firstpage :
833
Lastpage :
838
Abstract :
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizing such clock scheduler may be considerable if registers are placed without considering assigned skews. Focusing on this issue, in this paper, we propose a skew scheduling-aware register placement algorithm that enables clock tree optimization by considering domains assigned to registers in placement. Our experimental results show that the proposed approach remarkably decreases clock wire length and clock network power consumption at the cost of a slight increase in total wire length.
Keywords :
circuit optimisation; clocks; low-power electronics; phase shifters; clock network power consumption; clock tree optimization; clock wire length; multidomain clock skew scheduling-aware register placement; optimized clock distribution network; phase shifter; Clocks; Costs; Delay effects; Energy consumption; Integrated circuit interconnections; Processor scheduling; Registers; Scheduling algorithm; Sequential circuits; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
ISSN :
1530-1591
Print_ISBN :
978-1-4244-3781-8
Type :
conf
DOI :
10.1109/DATE.2009.5090778
Filename :
5090778
Link To Document :
بازگشت