DocumentCode :
2175026
Title :
Single ended 6T SRAM with isolated read-port for low-power embedded systems
Author :
Singh, Jawar ; Pradhan, Dhiraj K. ; Hollis, Simon ; Mohanty, Saraju P. ; Mathew, J.
Author_Institution :
Dept. of Comput. Sci., Univ. of Bristol, Bristol
fYear :
2009
fDate :
20-24 April 2009
Firstpage :
917
Lastpage :
922
Abstract :
This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-VDD and low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An 8Kbit SRAM module with the proposed and standard 6T bitcells is simulated, including full blown parasitics using BPTM, 65 nm CMOS technology node to evaluate and compare different performance parameters. The active power dissipation in the proposed 6T design is 28% and 25% less, compared to standard 6T and 8T SRAM modules respectively.
Keywords :
CMOS memory circuits; SRAM chips; embedded systems; transistor circuits; CMOS technology; SRAM module; active power dissipation; isolated read-port; memory size 8 KByte; parasitics; six-transistor single- ended static random access memory bitcell; size 65 nm; static noise margin; Batteries; CMOS technology; Capacitance; Computer science; Embedded system; Energy consumption; Inverters; Random access memory; Stability; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
ISSN :
1530-1591
Print_ISBN :
978-1-4244-3781-8
Type :
conf
DOI :
10.1109/DATE.2009.5090796
Filename :
5090796
Link To Document :
بازگشت