Design of PLL-Based Synchronous PWM Oscillator in Class-D Power Amplifier

Author

Zhao Fei ; Xu Yongbin ; Xu Yong ; Guan Yu

Author_Institution

Inst. of Meteorol., PLA Univ. of Sci. & Technol., Nanjing, China

fYear

2009

fDate

17-19 Oct. 2009

Firstpage

1

Lastpage

4

Abstract

To minimize the effect of cross talk in monolithic stereo class D power amplifier, one improved scheme in stereo application with dual-chips is presented. Pulse Width Modulation (PWM) in master and salve chip should be synchronized each other for decreasing distortion, so a phase locked loop (PLL) -based synchronous oscillator is designed in class-D power amplifier chip. When power supply is 5.5 V, input frequency is 1 KHz and output power is 3.7 W in 4 Ohm load, the total harmonic noise (THD) of amplifier is less than 1% and efficiency is about 90%. The class-D amplifier quiescent current is 1.9 mA and shutdown quiescent current is 0.5 muA.

Keywords

audio-frequency amplifiers; phase locked loops; phase locked oscillators; power amplifiers; pulse width modulation; cross talk effect; frequency 1 kHz; master-salve chip; monolithic stereo class D power amplifier; phase locked loop; power 3.7 W; pulse width modulation; resistance 4 ohm; synchronous PWM oscillator; total harmonic noise; voltage 5.5 V; Frequency synchronization; Oscillators; Phase distortion; Phase locked loops; Phase modulation; Power amplifiers; Pulse amplifiers; Pulse width modulation; Pulsed power supplies; Space vector pulse width modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Image and Signal Processing, 2009. CISP '09. 2nd International Congress on

Conference_Location

Tianjin

Print_ISBN

978-1-4244-4129-7

Electronic_ISBN

978-1-4244-4131-0

Type

conf

DOI

10.1109/CISP.2009.5304837

Filename

5304837