Title :
Radiation hardened SOI CMOS and 1M SRAM
Author :
Fechner, P.S. ; Dougal, G.D. ; Sullwold, J.G. ; Swanson, R. ; Shaw, G.A. ; Liu, S.T. ; Yue, C.S.
Author_Institution :
Solid State Electron. Center, Honeywell Inc., Plymouth, MN, USA
Abstract :
Describes 2M rad(SiO2) radiation hardened partially depleted SOI CMOS technology used to fabricate a 1M SRAM on full dose SIMOX (Separation by IMplantation of OXygen) wafers with an oxygen ion dose of 1.7×1018/cm2 at 190 keV. They were annealed by Honeywell at 1325 °C resulting in buried oxide thickness of approximately 370 nm and post CMOS processing silicon thickness of approximately 190 nm. Prior to processing, the SIMOX wafers are screened to achieve surface defect density of <0.2 per cm2, HF defect density of <1 per cm2, and background doping of <2×1016 per cm3
Keywords :
CMOS memory circuits; SIMOX; SRAM chips; annealing; integrated circuit measurement; radiation hardening (electronics); 1 Mbit; 1325 degC; 190 keV; 190 nm; 2 Mrad; 370 nm; SRAM; Si:O; annealing; background doping; buried oxide thickness; full dose SIMOX; partially depleted SOI CMOS technology; post CMOS processing thickness; radiation hardened circuits; surface defect density; CMOS process; CMOS technology; Leakage current; MOS devices; MOSFETs; Radiation hardening; Random access memory; Temperature distribution; Testing; Threshold voltage;
Conference_Titel :
SOI Conference, 1997. Proceedings., 1997 IEEE International
Conference_Location :
Fish Camp, CA
Print_ISBN :
0-7803-3938-X
DOI :
10.1109/SOI.1997.634988