Reducing power consumption during test application by test vector ordering

Author

Girard, P. ; Landrault, C. ; Pravossoudovitch, S. ; Severac, D.

Author_Institution

Lab. d´´Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

296

Abstract

This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on a re-ordering of the vectors in the test sequence to minimize the switching activity of the circuit during test application. Our technique uses the Hamming distance between test vectors and guarantees a decrease in power consumption and heat dissipation without modifying the initial fault coverage. Results of experiments are presented at the end of this paper and shows a reduction of the circuit activity in the range from 8.2 to 54.1% during test application

Keywords

VLSI; automatic testing; digital integrated circuits; integrated circuit testing; vectors; Hamming distance; IC testing; VLSI integrated circuits; heat dissipation reduction; power consumption reduction; power ratings; switching activity minimisation; test application; test sequence; test vector ordering; Batteries; Circuit faults; Circuit testing; Energy consumption; Hamming distance; Integrated circuit testing; Logic testing; Packaging; Power dissipation; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706917

Filename

706917