Input-Driven Reconfiguration for Area and Performance Adaption of Reconfigurable Accelerators

Attaching a reconfigurable loop accelerator to a processor for improving the performance and the efficiency of the system, which can be further enhanced by unrolling the loop to change its parallelism in a better way, is a promising development. The more a loop is unrolled, the wider the reconfigurable area that is exposed. However, the utilization of a loop accelerator is highly linked with the input. Also, in some situations, one will be wasting area to overunroll the loop. With a focus on the area and the performance balance, this paper proposes a dynamically adaptive reconfigurable accelerator framework for the processor/RL architecture. In the framework, reconfiguration of the accelerator is driven by the input. An accelerator selection model is presented for selecting an accelerator at run time among the predefined input patterns. Also, with the help of a detailed illustration of a bzip2 case study, experimental results were provided for the feasibility of the approach, which showed that up to 69.21% reconfigurable area is saved at a cost of 2.63% performance slowdown in the best case.