Title :
Sharing power distribution networks for enhanced power integrity by using Through-Silicon-Via
Author :
Pak, Jun So ; Kim, Jaemin ; Lee, Junho ; Lee, Hyungdong ; Park, Kunwoo ; Kim, Joungho
Author_Institution :
Dept. of Electr. Eng., Terahertz Interconnection & Package Lab., Daejeon, South Korea
Abstract :
This paper presents the excellent enhancement of power integrity (PI) by using through-silicon-via (TSV), which gives very small inductance to power distribution network (PDN) and consequently makes PDN impedance very low by sharing PDNs of 3-dimensionally (3-D) stacked chips. In this paper, the enhanced PI is shown by comparing that of wire-bonding applied 3-D stacked chips. A single SG (Signal/Ground)-TSV-pair shows very small serial inductance (< 30 pH) due to its small height (80 ¿m) and shunt capacitance (> 4 pF) due to its thin SiO2 (0.2 ¿m) between TSV and silicon substrate. In TSV applied 3-D multi-stacked chips case for high frequency application, the stability of PI becomes better than any other interconnection methods.
Keywords :
capacitance; distribution networks; inductance; integrated circuit interconnections; lead bonding; system-in-package; 3-D multi-stacked chip; 3-dimensionally stacked chips; impedance; interconnection; power distribution network; power integrity; serial inductance; shunt capacitance; system in package; through-silicon-via; wire bonding; Consumer electronics; Electronics packaging; Impedance; Inductance; Personal digital assistants; Power systems; Semiconductor device packaging; Silicon; Substrates; Through-silicon vias;
Conference_Titel :
Advanced Packaging and Systems Symposium, 2008. EDAPS 2008. Electrical Design of
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-2633-1
Electronic_ISBN :
978-1-4244-2634-8
DOI :
10.1109/EDAPS.2008.4735985
