Title :
32-bit cyclic redundancy codes for Internet applications
Author_Institution :
Dept. of Electron. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
Standardized 32-bit cyclic redundancy codes provide fewer bits of guaranteed error detection than they could, achieving a Hamming Distance (HD) of only 4 for maximum-length Ethernet messages, whereas HD=6 is possible. Although research has revealed improved codes, exploring the entire design space has previously been computationally intractable, even for special-purpose hardware. Moreover, no CRC polynomial has yet been found that satisfies an emerging need to attain both HD=6 for 12K bit messages and HD=4 for message lengths beyond 64 Kbits. This paper presents results from the first exhaustive search of the 32-bit CRC design space. Results from previous research are validated and extended to include identifying all polynomials achieving a better HD than the IEEE 802.3 CRC-32 polynomial. A new class of polynomials is identified that provides HD=6 up to nearly 16K bit and HD=4 up to 114K bit message lengths, providing the best achievable design point that maximizes error detection for both legacy and new applications, including potentially iSCSI and application-implemented error checks.
Keywords :
IEEE standards; Internet; cyclic codes; error detection; error detection codes; local area networks; polynomials; redundancy; telecommunication standards; 32 bit; Hamming Distance; IEEE 802.3; Internet applications; application-implemented error checks; cyclic redundancy codes; error detection; guaranteed error detection; iSCSI; maximum-length Ethernet messages; message lengths; polynomial; special-purpose hardware; Computer errors; Computer networks; Cyclic redundancy check; Ethernet networks; Hamming distance; Hardware; High definition video; Internet; Memory; Polynomials;
Conference_Titel :
Dependable Systems and Networks, 2002. DSN 2002. Proceedings. International Conference on
Print_ISBN :
0-7695-1101-5
DOI :
10.1109/DSN.2002.1028931
