DocumentCode
2176022
Title
SEU-aware resource binding for modular redundancy based designs on FPGAs
Author
Golshan, Shahin ; Bozorgzadeh, Eli
Author_Institution
Comput. Sci. Dept., Univ. of California, Irvine, CA
fYear
2009
fDate
20-24 April 2009
Firstpage
1124
Lastpage
1129
Abstract
Although Triple Modular Redundancy (TMR) has been widely used to mitigate single event upsets (SEUs) in SRAM-based FPGAs, SEU-caused bridging faults between the TMR modules do not guarantee correctness of TMR design under SEU. In this paper, we present a novel approximation algorithm for resource binding on scheduled datapaths at the presence of TMR, which aims at containment of each SEU within a single replica of tripled operations. The key challenges are to avoid resource sharing between modular redundant operations and also to reduce the possibility of TMR masking breaches in resource allocation. We introduce the notion of vulnerability gap during resource sharing to potentially reduce the effort for white space allocation at the physical design stage in order to avoid bridging faults between TMR resources. The experimental results show that our proposed resource binding algorithm, followed by floorplanner, reduces the potential of TMR breaches by 20%, on average.
Keywords
field programmable gate arrays; logic design; redundancy; FPGA; SEU-aware resource binding; floorplanner; single event upsets; triple modular redundancy; vulnerability gap; Circuit faults; Computer errors; Field programmable gate arrays; High level synthesis; Redundancy; Resource management; Routing; Single event transient; Single event upset; White spaces; FPGA; Triple modular redundancy; high level design; single event upset;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location
Nice
ISSN
1530-1591
Print_ISBN
978-1-4244-3781-8
Type
conf
DOI
10.1109/DATE.2009.5090832
Filename
5090832
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