Title :
7 Gbit/s measurements on a 0.8 μm CMOS line-receiver
Author :
Johansson, Henrik O.
Author_Institution :
Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden
fDate :
31 May-3 Jun 1998
Abstract :
Successful sampling of every 32nd bit in a 7 Gbit/s data stream has been shown with a 0.8 μm CMOS circuit which is based on parallel sampling. The input bandwidth of the chip is the suspected bit rate limiting factor. The input bandwidth is mainly set by the wire characteristic impedance and the input capacitance of the chip. Half of a 5 Gbit/s data stream has been received by the same circuit. This indicates that (full) reception of 5 Gbit/s data-streams is possible. The bit rate limiting factor in this case is the accuracy and jitter of the control-clocks to the sampling-switches
Keywords :
CMOS analogue integrated circuits; analogue processing circuits; data communication equipment; digital communication; jitter; receivers; sample and hold circuits; signal sampling; 0.8 micron; 5 Gbit/s; 7 Gbit/s; CMOS line-receiver; Gbit/s data stream; bit rate limiting factor; control-clocks; input capacitance; jitter; parallel sampling; sampling-switches; wire characteristic impedance; Circuit testing; Clocks; Delay lines; Frequency; Resistors; Sampling methods; Signal generators; Switches; Switching circuits; Voltage control;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706920
