Title :
Low-voltage 0.35 μm CMOS/SOI technology for high-performance ASIC´s
Author :
Adan, A.O. ; Naka, T. ; Kaneko, S. ; Urabe, D. ; Higashi, K. ; Kagisawa, A.
Author_Institution :
VLSI Dev. Lab., Sharp Corp., Tenri, Japan
Abstract :
A 0.35 μm CMOS process for low-voltage, high-performance ASIC´s, implemented on ultra-thin SOI (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1.5v are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1.5v supply voltage, demonstrating the excellent performance of this technology
Keywords :
CMOS integrated circuits; SIMOX; application specific integrated circuits; integrated circuit technology; phase locked loops; 0.35 micron; 1.5 V; 1.6 GHz; ASIC; PLL circuit; low-voltage CMOS/SOI technology; power dissipation; salicide dual-gate process; shallow SIMOX wafer; Application specific integrated circuits; CMOS process; CMOS technology; Capacitance; Capacitors; Frequency; Integrated circuit interconnections; Power dissipation; Resistors; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606659
