Title :
A regenerator section overhead processing chip set for STM-64
Author :
Lee, Seog-Hoon ; Kim, Jong-Ho ; Kim, Dong-Hyun
Author_Institution :
Electron. & Telecommun. Res. Inst., Taejon, South Korea
Abstract :
A chip set has been designed for the 10 Gb/s SDH-based optical transmission system and developed using GaAs gate array technology. The features supported by the chip set include 8:1 multiplexing and demultiplexing, frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, and B1 byte insertion and error detection. This paper describes the architecture, implementation, and experimental results of the chip set, and parallel circuit design technologies suitable for the very high-speed SDH-based optical transmission system
Keywords :
MESFET integrated circuits; application specific integrated circuits; demultiplexing equipment; digital signal processing chips; error detection; field effect digital integrated circuits; gallium arsenide; logic arrays; multiplexing equipment; optical communication equipment; parallel architectures; synchronous digital hierarchy; 0.6 mum; 10 Gbit/s; 32 bit; 32-bit parallel scrambling; 8:1 multiplexing; B1 byte insertion; GaAs; GaAs MUX ASIC; GaAs gate array technology; SDH-based optical transmission system; STM-64; architecture; demultiplexing; descrambling; enhancement/depletion mode MESFET technology; error detection; frame alignment word insertion; parallel circuit design technologies; regenerator section overhead processing chip set; very high-speed SDH-based optical transmission system; Application specific integrated circuits; Clocks; Gallium arsenide; High speed optical techniques; Multiplexing; Optical signal processing; Repeaters; Signal processing; Synchronous digital hierarchy; Timing;
Conference_Titel :
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-3702-6
DOI :
10.1109/APCAS.1996.569250
