Title :
Modeling of chip-package-PCB hierarchical power distribution network based on segmentation method
Author :
Kim, Jaemin ; Shim, Jongjoo ; Pak, Jun So ; Kim, Joungho
Author_Institution :
Sch. of EECS, Terahertz Interconnection & Package Lab., Guseong-dong, South Korea
Abstract :
In this paper, a new modeling method for fast estimation of impedance profile in system-level PDN containing not only chip, package and PCB-level PDNs but also various interconnections such as via, ball and bond-wire is proposed. The basic modeling method is segmentation method and FDTD based EM solver and a series of analytic modeling methods such as resonant cavity model and lumped circuit model are used. The proposed modeling method is successfully verified by measurement up to 20 GHz in frequency domain.
Keywords :
chip scale packaging; finite difference time-domain analysis; lead bonding; lumped parameter networks; printed circuits; EM solver; FDTD; analytic modeling methods; ball wire; bond-wire; chip-package-PCB hierarchical power distribution network; impedance profile; lumped circuit model; resonant cavity model; segmentation method; Bonding; Finite difference methods; Impedance; Integrated circuit interconnections; Packaging; Power system interconnection; Power system modeling; Power systems; Resonance; Time domain analysis;
Conference_Titel :
Advanced Packaging and Systems Symposium, 2008. EDAPS 2008. Electrical Design of
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-2633-1
Electronic_ISBN :
978-1-4244-2634-8
DOI :
10.1109/EDAPS.2008.4736005
