DocumentCode :
2176593
Title :
Communication energy constrained spare core on NoC
Author :
Kumar, B.Naresh ; Sharma, Dheeraj
Author_Institution :
Reddy Dept. of Electronics and Communication Engineering, NIT Goa
fYear :
2015
fDate :
June 29 2015-July 2 2015
Firstpage :
21
Lastpage :
24
Abstract :
In Multi-processor System on-chip, each processor produce and consumes high data. Transporting of data is a crucial role in MPSOC, Therefore Network on Chip (NoC) preferred as a communication medium, because good communication performance and fast operating. While considering NoC Architectural some temporary, permanent faults occur in the core. This paper propose the placement of spare core and its communication energy constraints, we investigated energy metrics in place of spare core and finally saving communication energy leads to previous algorithms.
Keywords :
Algorithm design and analysis; Computer architecture; Energy efficiency; Fault tolerance; Fault tolerant systems; Resource management; System-on-chip; Core; Fault tolerance; Network on Chip (NoC);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Ph.D. Research in Microelectronics and Electronics (PRIME), 2015 11th Conference on
Conference_Location :
Glasgow, United Kingdom
Type :
conf
DOI :
10.1109/PRIME.2015.7251084
Filename :
7251084
Link To Document :
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