Test exploration and validation using transaction level models

Author

Kochte, Michael A. ; Zoellin, Christian G. ; Imhof, Michael E. ; Khaligh, Rauf Salimi ; Radetzki, Martin ; Wunderlich, Hans-Joachim ; Carlo, Stefano Di ; Prinetto, Paolo

Author_Institution

Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart

fYear

2009

fDate

20-24 April 2009

Firstpage

1250

Lastpage

1253

Abstract

The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally well.

Keywords

integrated circuit modelling; logic testing; system-on-chip; TLM communication-centric view; TLM stimuli; systems-on-chip approach test exploration stratergy; transaction level model testing; Automatic testing; Computational modeling; Concurrent computing; Context modeling; Design for testability; Discrete event simulation; Object oriented modeling; Scheduling; Space exploration; System testing; Test of systems-on-chip; design-for-test; transaction level modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.

Conference_Location

Nice

ISSN

1530-1591

Print_ISBN

978-1-4244-3781-8

Type

conf

DOI

10.1109/DATE.2009.5090856

Filename

5090856