Clocking Links in Multi-chip Packages: A Case Study

This brief note presents a case study for clocking links in multi-chip packages. A particular co-packaged multichip system design based on multi-Gbps silicon photonics global interconnect provides the context for our study of near-short range links, and we explore its design space. A preliminary exploration of phase noise suggests that the links should be clocked mesochronously, with an optically distributed full-rate clock and using local phase adjustment at each receiver.