DocumentCode
2177372
Title
A delay estimation method using reduced model of RLC interconnects
Author
Park, Chang-Woo ; Jeong, Moon-Sung ; Kim, Ki-Young ; Kim, Seok-Yoon
Author_Institution
Grad. Sch., Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea
fYear
2008
fDate
10-12 Dec. 2008
Firstpage
222
Lastpage
225
Abstract
This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, yet precise. The proposed method can calculate the delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model RLC interconnects. The results using the proposed method for RLC circuits show that the average relative error is within 10% in comparison with HSPICE simulation results.
Keywords
RLC circuits; delay estimation; integrated circuit interconnections; RLC interconnects; VLSI systems; delay estimation method; delay time calculation; Circuit analysis; Computer science; Delay effects; Delay estimation; Distributed parameter circuits; Frequency; Inductance; Integrated circuit interconnections; RLC circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Packaging and Systems Symposium, 2008. EDAPS 2008. Electrical Design of
Conference_Location
Seoul
Print_ISBN
978-1-4244-2633-1
Electronic_ISBN
978-1-4244-2634-8
Type
conf
DOI
10.1109/EDAPS.2008.4736040
Filename
4736040
Link To Document