Title :
VLSI design of a quaternary carry ripple adder
Author :
Razavi, Hassan M. ; Kaylani, Tarek
Author_Institution :
North Carolina Univ., Charlotte, NC, USA
Abstract :
The design of a CMOS quaternary carry ripple adder is presented. The adder uses a single 5-V power supply. Layout and simulations for 4-, 8-, and 16-stage adders were done with MCNC (Microelectric Center of North Carolina) tools for VLSI design. The simulation results are compared with results for equivalent binary adders in terms of speed, chip area, power dissipation, number of transistors, and noise margin. The study indicates a speed advantage for the quaternary adder as the number of stages are increased
Keywords :
CMOS integrated circuits; VLSI; adders; CMOS IC; Microelectric Center of North Carolina; VLSI; chip area; noise margin; power dissipation; quaternary carry ripple adder; Adders; Digital systems; Logic design; Microelectronics; Power dissipation; Power supplies; Propagation delay; Switching circuits; Very large scale integration; Voltage;
Conference_Titel :
System Theory, 1989. Proceedings., Twenty-First Southeastern Symposium on
Conference_Location :
Tallahassee, FL
Print_ISBN :
0-8186-1933-3
DOI :
10.1109/SSST.1989.72513
