DocumentCode :
2177544
Title :
Optimization of DRAM sense amplifiers for the gigabit era
Author :
Parke, Stephen A.
Author_Institution :
Dept. of Electr. Eng., Boise State Univ., ID, USA
Volume :
1
fYear :
1997
fDate :
3-6 Aug 1997
Firstpage :
209
Abstract :
This paper reviews sense amplifier design challenges as DRAM densities are increased beyond a gigabit. Various proposed solutions for maintaining high performance and sensitivity, while reducing the array voltage are reviewed. Preamplification, body-effect control, Vt mismatch cancellation, and two revolutionary solutions are presented and discussed
Keywords :
DRAM chips; circuit optimisation; compensation; differential amplifiers; DRAM sense amplifiers; array voltage reduction; body-effect control; dynamic RAM; gigabit DRAMs; high performance; preamplification; sensitivity; threshold voltage mismatch cancellation; Boosting; Charge transfer; Circuits; Degradation; Isolators; Latches; MOS capacitors; MOS devices; Random access memory; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-7803-3694-1
Type :
conf
DOI :
10.1109/MWSCAS.1997.666070
Filename :
666070
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2177544
بازگشت