• DocumentCode
    2177622
  • Title

    Scalable Adaptive Scan (SAS)

  • Author

    Chandra, Anshuman ; Kapur, Rohit ; Kanzawa, Yasunari

  • Author_Institution
    Synopsys, Inc., Mountain View, CA
  • fYear
    2009
  • fDate
    20-24 April 2009
  • Firstpage
    1476
  • Lastpage
    1481
  • Abstract
    Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarchical implementations need test access mechanisms that keep the isolation between the different tests applied through the different compressors and decompressors. In this paper we discuss a test access mechanism for Adaptive Scan that addresses the problem of reducing test data and test application time in a hierarchical and low pin count environment. An active test access mechanism is used that becomes part of the compression schemes and unifies the test data for multiple CODEC implementations. Thus, allowing for hierarchical DFT implementations with flat ATPG.
  • Keywords
    automatic test pattern generation; data compression; design for testability; electronic design automation; integrated circuit manufacture; integrated circuit testing; CODEC; flat ATPG; hierarchical DFT; low pin count environment; manufacturing test cost; scalable adaptive scan; scan compression; test access mechanism; Automatic test pattern generation; Codecs; Compressors; Costs; Design for testability; Isolation technology; Logic design; Logic testing; Manufacturing; Synthetic aperture sonar;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
  • Conference_Location
    Nice
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-3781-8
  • Type

    conf

  • DOI
    10.1109/DATE.2009.5090896
  • Filename
    5090896