Analyzing the impact of substrate noise on embedded analog-to-digital converters

Author

Zinzius, Yann ; Gielen, Georges ; Sansen, Willy

Author_Institution

Dep. Elektrotechniek, Katholieke Univ., Leuven, Belgium

fYear

2002

fDate

2002

Firstpage

82

Lastpage

85

Abstract

This paper presents the analysis and measurements of the impact of digital substrate noise on embedded Analog-to-Digital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D converter. To confirm the analysis the substrate noise has also been measured on a test chip designed in a 0.35 μm heavily-doped-substrate CMOS technology. From the measurements it was deduced that SNR and the effective number of bits are reduced by 20%.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit noise; jitter; system-on-chip; 0.35 micron; A/D converter; MOS transistor model; SNR; SoC; analog design; analog-to-digital converters; digital substrate noise; embedded ADCs; equivalent output signal jitter; heavily-doped-substrate CMOS technology; regenerative comparator; Analog-digital conversion; CMOS technology; Circuit noise; Equations; MOSFETs; Noise generators; Noise measurement; Semiconductor device measurement; Topology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems for Communications, 2002. Proceedings. ICCSC '02. 1st IEEE International Conference on

Print_ISBN

5-7422-0260-1

Type

conf

DOI

10.1109/OCCSC.2002.1029050

Filename

1029050